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- C. Mukherjee, C. Maneux, J. Pezard, and G. Larrieu, « 1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors », Proc. 47th IEEE European Solid-State Device Research Conference (ESSDERC 2017), Proc. of the 47th IEEE European Solid-State Device Research Conference, Leuven, Belgium, September 2017. DOI: 10.1109/ESSDERC.2017.8066585
- C. Mukherjee, G. Larrieu, C. Maneux, « Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors », EuroSOI-ULIS, Caen, France, Virtual conference September, 2020. DOI: hal preprint : hal-02869216, version 1
- C. Mukherjee, M. Deng, F. Marc, C. Maneux, A. Poittevin, I. O’Connor, S. Le Beux, A. Kumar, A. Lecestre, G. Larrieu, « 3D logic cells design and results based on Vertical NWFET technology including tied compact model », VLSI-SoC 2020, 28th IFIP/IEEE International Conference on Very Large Scale Integration, 5-9 October 2020, Salt Lake City, UT, USA, 2020. DOI: arXiv preprint : https://arxiv.org/abs/2005.14039
- [INVITED] C. Maneux, I. O’Connor, S. Le Beux, G. Larrieu, “New logic paradigms based on vertical NanoWire FET: The coming LEGO technology”, École d’hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes, FETCH, 27 janv. 2019, Louvain la neuve, Belgique.
- [INVITED] I. O’Connor, A. Poittevin, A. Bosio, S. Le Beux, C. Marchand, G. Larrieu, C. Maneux, « Vertical nanowire FETs and their impact on 3D computing architectures », Invited paper, 28th IFIP/IEEE International Conference on Very Large Scale Integration ,VLSI-SoC 2020, 5-9 October 2020, Salt Lake City, UT, USA
